High Speed Serial Link Transmitter using Multi-level (4-PAM) Signaling in 0.18 μm CMOS|RISS 상세보기

다국어 초록 (Multilingual Abstract)

A 8 Gb/s multilevel pulse amplitude modulation (PAM) transmitter for chip to chip communication is proposed. By reducing symbol rate a half with 4-PAM, high speed in data transmission is achieved. Pre-switching the output driver？s current sources enables to decrease glitches of the output. In addition, the transmitter transmits output by current-mode instead of voltage-mode to increase switching speed of driver. The transmitter output driver is designed with a 4:1 multiplexer to reduce required input data frequency to 1/4 of the symbol rate, or 500 MHz. 27-1 pseudo random bit sequence (PRBS) generator is made to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek 0.18 ？m CMOS technology and achieves 4 GS/s (8 Gb/s), a data eye opening with a height > 160 mV with 1.8 V supply voltage. The 0.7 ？ 0.6 mm2 chip consumes 98 mW for 8 Gb/s transmission.

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국문 초록 (Abstract)

본 논문은 8 Gb/s multilevel pulse amplitude modulation (PAM) serial link transmitter에 관하여 제안하였다. 제한된 channel bandwidth를 극복하기 위해 4-PAM을 사용하여 data를 전송하였으며 4-PAM은 4개의 level로 각기 data 2 bit씩을 나타내므로 필요한 전송 frequency는 반으로 줄어 2 GHz의 clock으로 8 Gb/s의 전송 속도가 가능해졌다. 제안된 4-PAM transmitter는 전압 output 대신 전류 output을 생성하며 이로 인해 driver의 switching time이 빨라져서 더 높은 속도의 transmitter를 구현할 수 있었다. 27-1 pseudo random bit sequence (PRBS) 생성기는 built-in self test (BIST)를 하기위해 on-chip으로 설계되었다. 본 연구는 동부 하이텍 0.18 µm CMOS 공정을 통하여 설계되었으며 1.8 V supply voltage에서 eye 크기가 160 mV 이었으며 최대 동작 속도는 8 Gb/s이다. 칩 전체 면적은 0.7 × 0.6 mm2이며 전력 소모는 98 mW이다.

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본 논문은 8 Gb/s multilevel pulse amplitude modulation (PAM) serial link transmitter에 관하여 제안하였다. 제한된 channel bandwidth를 극복하기 위해 4-PAM을 사용하여 data를 전송하였으며 4-PAM은 4개의 level로 각기...

목차 (Table of Contents)

Chapter 1 Introduction = 12
1.1 Motivation = 12
1.2 Organization of Thesis = 13
Chapter 2 Limitation and Architecture of the Signaling System = 14
2.1 Signaling Techniques = 14

Chapter 1 Introduction = 12
1.1 Motivation = 12
1.2 Organization of Thesis = 13
Chapter 2 Limitation and Architecture of the Signaling System = 14
2.1 Signaling Techniques = 14
2.1.1 Traditional Large-Swing Voltage-Mode Signaling = 15
2.1.2 Low-swing Current-mode Incident Wave Signaling = 17
2.2 Limits of Electrical Signaling = 18
2.2.1 Electronic Limitations = 18
2.2.2 Transmission Medium Limitations = 20
2.3 Selected Modulation = 22
2.3.1 4-Level Pulse Amplitude Modulation (4-PAM) = 22
2.3.2 Coding = 24
Chapter 3 System Implementation = 25
3.1 Transmitter = 25
3.1.1 PRBS Generator = 27
3.1.2 Encoder = 28
3.1.3 Multiplexer = 30
3.1.4 4-PAM Current-mode Driver = 32
3.2 Simulation Results = 34
3.2.1 PRBS Generator Simulation Result = 34
3.2.2 Encoder and Multiplexer Simulation Results = 35
3.2.3 Transmitter Simulation Results = 37
Chapter 4 Measurement Results and Discussion = 39
4.1 Measurement Setting = 39
4.1.1 Chip Layout and Test-board = 39
4.1.2 Measurement Setup = 41
4.2 Measurement Results = 42
Chapter 5 Conclusions = 47
Bibliography = 49
List of Figures
Figure 1. A CMOS inverter applies a logic level of 1 to a line: Wave form at the far end of the line = 5
Figure 2. A point-to-point, low-swing, incident-wave system = 6
Figure 3. Eye diagram showing limitations on signaling rate = 8
Figure 4. Model of lossy T line = 9
Figure 5. A 4-PAM eye diagram with finite transition times = 12
Figure 6. Linear versus Gray code mapping = 13
Figure 7. Block diagram of transmitter = 15
Figure 8. Selector of encoder's input = 16
Figure 9. PRBS generator = 17
Figure 10. Architecture of encoder = 18
Figure 11. 2:1 Multiplexer with timing latches = 19
Figure 12. 4:1 Multiplexer = 20
Figure 13. Architecture of 4-PAM 　current-mode driver = 22
Figure 14. Details of driver basic unit = 22
Figure 15. Output signals of PRBS generator = 23
Figure 16. Output signals of encoder = 24
Figure 17. Output signals of 4:1 multiplexer = 25
Figure 18.4-level output of transmitter at 4.8 Gb/s = 26
Figure 19. Eye-diagram of transmitter at 4.8 Gb/s = 26
Figure 20. 4-level output of transmitter at 8 Gb/s = 27
Figure 21. Eye-diagram of transmitter at 8 Gb/s = 27
Figure 22. Full chip die picture = 29
Figure 23. Chip on board for measurements = 29
Figure 24. Measurement environment = 31
Figure 25. Output of 4-PAM transmitter at 4.8 Gb/s = 32
Figure 26. Eye-diagram of 4-PAM transmitter at 4.8 Gb/s = 32
Figure 27. Output of 4-PAM transmitter at 6.4 Gb/s = 32
Figure 28. Eye-diagram of 4-PAM transmitter at 6.4 Gb/s = 33
Figure 29. Output of 4-PAM transmitter at 8 Gb/s = 33
Figure 30. Eye-diagram of 4-PAM transmitter at 8 Gb/s = 33
List of Tables
Table 1. Encoder mapping table = 18
Table 2. Measurement and simulation results = 34
Table 3. Measurement results with other works = 35

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High Speed Serial Link Transmitter using Multi-level (4-PAM) Signaling in 0.18 μm CMOS

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